1. Field of the Invention
The present invention relates to a method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device using such a device layer, the at least one semiconductor device layer comprising a compound semiconductor material and/or germanium, to a method for forming a semiconductor device using the method for removing impurities according to embodiments of the invention and to semiconductor devices thus obtained.
2. Description of the Related Technology
In state of the art semiconductor processing, novel materials have been introduced in the past years. Although silicon remains one of the main semiconductor materials for many applications, other materials have gained more interest. For example, germanium and II-VI and III-V materials have been introduced as materials which can advantageously be compared to silicon in terms of electrical or physical characteristics for dedicated applications. These materials can be used in various types of electronic and photonic systems, such as e.g. solar cells, light emitting diodes (LED), spin-electronics and quantum-well devices, III-V based field effect transistors (FET), III-V based heterojunction devices such as heterojunction bipolar transistors (HBT), III-V based high electron mobility transistors (HEMT) and high frequency devices or high power devices.
As II-VI and III-V semiconductor materials are formed by a combination of elements from different groups of the periodic table they are often referred to as compound semiconductors. Examples of such compound semiconductors may be (1) a combination of group III elements (B, Al, Ga, In) and group V elements (N, P, As, Sb, Bi) for compounds such as AlN, AlP, AlAs, GaN, GaP, GaAs, InP, InAs, InSb, AlInGaP, AlGaAs etc, or (2) a combination of group II elements (Zn, Cd, Hg) and group VI elements (O, S, Se, Te) for compounds such as ZnS, ZnSe, ZnTe, CdTe, HgTe, CdHgTe etc.
In manufacturing of semiconductor devices, contamination, more particularly metal contamination, is a well-known problem. The manufacturing of a semiconductor device is inevitably accompanied by inadvertent contamination, mainly by fast diffusing metals such as e.g. Cu, Fe, Ni, Co, which may be present in materials used during the manufacturing process when, for example, forming high-k gate dielectrics, a metal gate electrode or silicides. These contaminants may contaminate the semiconductor device layers and deteriorate the performance and reliability of the semiconductor device. For a given process flow for manufacturing semiconductor devices the presence of such contaminants in a semiconductor material which is part of the device, even in minute quantities, may determine the degree of performing performance of the semiconductor device. As silicon-based and III-V based devices are often fabricated in a same process flow, contaminants present in a layer of one material may contaminate layers formed in the other material. Therefore the impact of such contaminants on all semiconductor materials present in the process flow should be taken into account.
In silicon-based fabrication technology, methods are proposed in which these contaminants are trapped or neutralized so as to eliminate or substantially reduce their impact on the device performance and consequently to substantially reduce their impact on the yield of the fabrication process.
United States application US 2005/0239267 discloses a substrate manufacturing method for forming a substrate, e.g. a silicon-on-insulator (SOI), Ge, GaAs, AlGaAs or InP substrate, before using this substrate to fabricate semiconductor devices. A stack is formed of a gettering layer on an exposed surface of a first, e.g. silicon substrate which is bonded to an insulating layer, e.g. oxide layer, of a second, e.g. silicon substrate. By heating this stack impurities will diffuse from the first substrate towards the gettering layer. Thereafter the gettering layer is removed and the substrate, e.g. SOI substrate is fabricated. However, this method does not allow gettering impurities during the process of fabricating a semiconductor device.
United States application US 2004/0235264 discloses a method for creating gettering sites, i.e. sites for trapping contaminants, in a SOI (silicon-on-insulator) substrate. Relaxed silicon germanium regions are formed in the proximity of the device regions comprising a silicon-based device. These relaxed silicon germanium regions will generate defects which getter impurities from the adjacent silicon region. Although this method allows gettering contaminants during the process of manufacturing the semiconductor device, it doesn't allow gettering contaminants from semiconductor layers containing germanium or compound semiconductor materials because the thermal budget of the overall fabrication process of a semiconductor device using such germanium or compound semiconductor materials may be more limited compared to mainstream silicon technology.
United States application US 2003/0027406 discloses a method to getter impurities, in particular dopants, from a silicon device layer. A silicon-germanium layer with a germanium content of between 0% and 100% is formed in contact with the silicon device layer such that lattice defects like dislocations are created in the contact region. These defects will getter the impurities from the adjacent silicon layer. Although this method allows gettering impurities during the process of fabricating the semiconductor device (at high temperatures e.g. temperatures higher than 600° C.), it doesn't allow gettering of impurities from semiconductor layers containing germanium or compound semiconductor materials because the thermal budget of the overall fabrication process of a semiconductor device using such germanium or compound semiconductor materials may be more limited compared to mainstream silicon technology.
In “Experimental evidence for dislocation-related gettering in metamorphic InP/InGaAs high electron mobility transistor (HEMT) structures on GaAs substrate”, Journal of Applied Physics 100 (2006), 034505, Yuwei Liu et al. describe the use of a InGaAs gettering layer for gettering impurities from an InP layer. A dislocation-related gettering effect is obtained due to the presence of a dislocation network acting as gettering sink.
However, for III-V compound, II-VI compound or germanium-based semiconductor devices no or no efficient method is known to getter, during manufacturing of the semiconductor devices, impurities from device layers comprising III-V or other compound semiconductor materials or germanium. There is a need for methods to getter impurities, in particular metal impurities such as fast-diffusing species such as Fe, Co, Ni, from device layers containing III-V or other semiconductor compound materials or germanium. Hence there is a need to provide a semiconductor device comprising III-V or other semiconductor compound material based semiconductor regions which device can be fabricated with improved yield.